1. Field of the Invention
The present invention relates to circuitry for use in electronic systems having components operating in multiple time domains. More particularly, the present invention relates to circuitry for generating clock signals of varying frequency for use by different components within processor systems.
2. Art Background
Computer systems and other microprocessor controlled systems are generally divided into a group of components. These components are generally driven by a common "clock" or signal line carrying a signal that varies at a predetermined frequency. The phases of the clock signal are used for sequencing logic in integrated circuits, as well as for enabling memory arrays and other components in a computer system. The clock signal is provided to the various components in the computer system and components typically carry out their operation or set of operations during one or more clock cycles.
In the past, it has been quite common for all the components of the computer system to be driven by the same clock reference signal. This has required that computer designers design computer systems around a target operating clock frequency. Systems designed to operate at a single clock frequency are difficult to upgrade with components that operate at different clock frequencies. In order to accommodate faster or slower components while still supporting the "standard" components, modifications are required for the clock generation hardware. Modifying the clocking hardware results in additional expense to upgrade, less design reuse and longer time periods between design and marketing.
In those computer and microprocessor controlled systems where some components operate with faster clock cycles than others, the hardware that propagates the reference clock signal to the components have had to be sensitive to introducing a clock skew. Skew refers to the phase difference between the reference clock and the clock signal seen by each of the components. These offsets may occur due to propagation delays in the circuitry. As clock frequencies increase, the allowable error margin to account for skew decreases. Frequency multiplication is traditionally performed using a simple and well-known circuit which utilizes a phase locked loop (PLL). A basic frequency multiplier using a PLL is described in Horowitz & Hill, The Art of Electronics, 2d ed. Cambridge University Press, 1989, p. 647. Such a circuit can generate only whole multiples of the input clock frequency, thereby not accounting for secondary clock frequencies which are not integer multiples of the reference clock.
In those computer and microprocessor systems where it is necessary that some components or peripherals be operated at slower clock frequencies than the reference clock, traditional division circuits have generally been limited to division by even integers and are usually hardwired for a specific division value. Additionally, these dividers have not always produced output clock signal exhibiting the desired 50/50 duty cycle. Division by odd integers have been problematic in that timing control to ensure clock edge alignment is difficult. One solution that has been used to perform odd division has been to double of the frequency using the multiplication scheme described above and then dividing by twice the value of the desired odd divisor. The problem with this implementation is that the divisor then must utilize a phase locked loop or other analog circuitry which can add great expense and complexity to an otherwise digital circuit. Further, introducing analog circuitry such as phase locked loops into an integrated circuit increases the expense of development and debug time for the circuit.
Today's highly integrated systems find the need for using a number of different clocking speeds to satisfy all of the components and peripherals involved. It would be advantageous, and is therefore an object of the present invention, to develop a programmable divider that is capable of performing even and odd divisions as well as being able to provide an output clock signal that exhibits a 50/50 duty cycle.